Wiring congestion in an area of a semiconductor chip leads to non-steiner wire lengths and possibly unwireable nets. Non-steiner wire lengths impede the process of timing closure as each pass of routing can result in different nets seeing increased wire load, thus leading to a different set of circuit paths which may need to be optimized to meet timing requirements.
Arbitrarily replacing the region to spread out circuits may relieve wiring congestion, but at the expense of timing as there is greater distance between the circuits. U.S. Pat. No. 5,218,551, “Timing Driven Placement”, describes a method of circuit placement which considers both timing and wiring congestion. Although this has the desired effect of prioritizing the placement of a timing critical circuit, the leverage of keeping a non-timing critical circuit outside a wiring congestion region is limited in that no circuit optimization or buffering is performed. U.S. Pat. No. 6,080,201, “Integrated Placement and Synthesis for Timing Closure of Microprocessors”, goes a step further by modifying the circuit implementation, or re-synthesizing, based on placement information and timing constraints. Although the placement algorithm inherently has wiring congestion as a metric, the re-synthesizing process is driven primarily by timing constraints as well as power and area reduction. Circuit buffering or repowering is not done with the intent of removing wire paths from a particular area so that a greater number of timing critical circuits can be grouped closer together in that region. U.S. Pat. No. 6,192,508, “Method For Logic Optimization For Improving Timing and Congestion During Placement in Integrated Circuit Design”, discusses the use of logic optimization to potentially relieve congestion through subsequent placement. The logic optimization techniques are applied to congested circuits in general, there is no assurance that the logic optimization on a specific circuit will give placement the flexibility to move that circuit out of its congested region without impacting timing.
Although in general a good approximation, the congestion metrics used by placement tools may not always accurately correspond to the wireability in a particular region as the actual wiring blockage map typically is not used in estimating the congestion. Additionally, it is common to switch to fatter than standard width wires on nets when iterating towards timing closure, thus taking up more wiring tracks. This impact on congestion is not fully known at the time of chip placement. Hence, it is possible to wind up with an area of wiring congestion during actual routing even if placement congestion estimates would not have predicted it.
The idea presented here is a method for identifying those wire routes which can be buffered and removed from a region of wiring congestion without inducing negative timing slacks. The added buffers and associated wire routes can then be moved from the congestion region without perturbation to the rest of the design.